I. Field of the Invention
The present invention relates to wireless communications. More particularly, the present invention relates to an improved method of achieving synchronization with, and identifying a received signal in an asynchronous code division multiple access (CDMA) system.
II. Description of the Related Art
The International Telecommunications Union recently requested the submission of proposed methods for providing high rate data and high-quality speech services over wireless communication channels. One of the proposals was issued by the European Telecommunications Standards Institute (ETSI), entitled xe2x80x9cThe ETSI UMTS Terrestrial Radio Access (UTRA) ITU-R RTT Candidate Submissionxe2x80x9d, hereafter referred to as WCDMA. The contents of these submissions is public record and is well known in the art, and describes the use of PERCH channels in a WCDMA system as discussed herein.
FIG. 1 illustrates the parts of a frame transmitted on the WCDMA PERCH channel by each base station in a WCDMA communication system used to permit the mobile station to acquire synchronization with the base station.
A frame is 10 milliseconds in duration and consists of 40,960 chips. A frame is divided into 16 slots, each slot having 2560 chips. Each slot can then be thought of as being divided into 10 consecutive parts, each part consisting of 256 chips. For the purposes of this disclosure, the 10 parts of each slot are numbered from 1 to 10, with 1 being the earliest transmitted 256 chips of each slot.
The first 256 chips (part 1) of each slot in the frame consist of two orthogonal sequences, which are transmitted on top of one another. The first of the two orthogonal sequences is the primary synchronization code (PSC) sequence. The PSC sequence is the same sequence for every slot and for every base station in a WCDMA system. The second of the two orthogonal sequences transmitted in part 1 is the secondary synchronization code (SSC). One of seventeen possible SSC sequences is transmitted in each slot.
Parts 2 through 5 of each slot include broadcast data such as the system identity of the transmitting base station and other information that is of general use to all mobile stations in communication with that base station. Parts 6 through 10 of each slot are used to carry a pilot signal that is generated in accordance with an Orthogonal Gold code as defined by the aforementioned UTRA standard.
Since the PSC and SSC signals are transmitted during the same 256-chip part of each frame, each is transmitted at half the power of the signals in the other parts. In other words, the PSC signal is transmitted at a power of 3 dB less than the signals in parts 2 through 10 of each slot. The SSC signal is also transmitted at xe2x88x923 dB compared to signals in parts 2 through 10. Though this makes PSC and SSC detection more difficult, it keeps the transmission signal power constant throughout each frame.
FIG. 2 illustrates the apparatus used to generate the PERCH channel used for initial system acquisition in the proposed WCDMA Third Generation communication system. Primary Synchronization code (PSC) generator 1 generates a predetermined 256 chip sequence that is used for the first stage of system acquisition described later herein. The PSC is the same for all base stations in the communication system and is punctured into the first 256 chips of each slot of each frame.
In WCDMA systems, each base station spreads its transmissions using an orthogonal Gold code. The generation of orthogonal Gold codes is well known in the art. In WCDMA, all of the Gold codes are generated using the same generator polynomial. There are a total of 512 possible timing offsets of the Gold code for a given base station. These offsets are measured with respect to the start of a frame and not with respect to any centralized timing signal. The time-offset Gold code is truncated at the end of each ten millisecond frame, and then repeats from the offset point at the start of each frame.
WCDMA base stations transmit a secondary synchronization code (SSC) that serves two functions. First, the secondary synchronization code is used to identify the frame timing of a base station. Second the secondary synchronization code provides a group identification (GI), which narrows down the orthogonal Gold code offset to a subset of sixteen of the possible 512 offsets. In the proposed WCDMA systems, there are 32 different Group Identities, each associated with a set of sixteen Gold code offsets.
The group identification is provided to SSC outer coder 2. The group identification is mapped to one of 32 possible 16 element code words wherein each of the elements takes on one of seventeen possible values. The code words are selected as comma free codes such that any cyclic shift of any of the code words results in a vector that is not a legitimate code word. The elements of the code word are then provided to SSC inner coder 3 which maps each of the elements of the code words into a 256 chip sequence. Each of the possible 256 chip SSC sequences into which an element of the code word can be mapped is orthogonal to any other sequences used to encode an element of a code word. Each of the possible 256 chip SSC sequences is also orthogonal to the 256 chip sequence used by the PSC. Each of the sixteen 256 chip SSC sequence is added to the PSC sequence punctured into the first 256 chips of part 1 of the slots in each frame.
The PSC sequence and the SSC sequence are summed in adder 6. Because the sequences are orthogonal to one another they can be distinguished from one another at the receiver and will not, in a single path analysis, interfere with one another. In addition, broadcast common data is punctured into parts 2 through 5 of each slot of the frame. The remaining 1280 chips (occupying parts 6 through 10) of the slots in each frame consist of the remaining unpunctured chips of the orthogonal Gold code sequence used to spread the transmissions from the base station. The first 1280 chips of the orthogonal Gold code sequence within each slot is punctured out by the PSC/SSC and common broadcast information.
FIG. 3 illustrates the current state of the art in acquiring synchronization in a WCDMA communication system. The signal is received at antenna 10 and provided to receiver (RCVR) 11. Receiver 11 down converts, amplifies and samples the received signal and provides the samples to Primary Synchronization code (PSC) detector 12. The PSC is redundantly transmitted in part 1 of each of the sixteen slots of each frame. The PSC is transmitted at a very low power using very weak coding that is prone to false detection. In order to reduce the probability of false detection to an acceptable level, currently contemplated systems accumulate three full frames of samples into a buffer.
The following description will assume that the sampling is 1xc3x97 and real samples only are taken. In reality the WCDMA system uses QPSK modulation so the sampling will be complex and oversampling is desirable to increase the likelihood of accurate detection.
Slot buffer 14 is a circular buffer that is capable of holding 2560 samples. The elements of slot buffer 14 are initialized to zero at the start of slot timing acquisition. The first 2560 samples are provided directly to slot buffer 14. Thereafter, the samples received over the remainder of three frame periods are summed in summer 13 with corresponding accumulated sample values stored in slot buffer 14 in accordance with equation (1) below:
ACCUM_SAMP(i)=ACCUM_SAMP(i)+NEW_SAMP(i+2560n),xe2x80x83xe2x80x83(1)
where i is a slot chip number between 0 and 2559, ACCUM_SAMP(i) is the ith value stored in slot buffer 14, NEW_SAMP(i) is the ith sample received and n is a slot number from 0 to 47 (corresponding to the number of slots in 3 full frames).
For the first 30 milliseconds of signal accumulation, switch 30 is set so that the values output by summer 13 are stored back into slot buffer 14. At the completion of the signal accumulation period, switch 30 moves so as to provide the output values from summer 13 to correlator 15. The function of correlator 15 is to detect the PSC sequence within the 2560 possible locations in slot buffer 14. It will be understood by one skilled in the art that slot buffer 14 is a circular buffer that allows wrap around addressing to test all possible hypotheses. Correlator 15 correlates 256 accumulated signal samples with the 256 chip PSC sequence and provides the resulting 2560 calculated correlation energies to maximum detector (MAX DETECT) 16. Maximum Detector 16 detects the point of highest correlation with the PSC sequence in the stored accumulated samples.
By detecting the PSC within the slots, the receiver has acquired slot level timing synchronization, whereby the receiver knows where each of the slots of the frame begin. The slot timing information is provided to multiplexer 31. In reality, the slot timing information would be provided to a control processor (not shown) that would control the operation of multiplexer 31 using the slot timing information.
The SSC is also transmitted at low energy and in order to attain sufficient confidence in the received signal would require accumulation of two redundantly transmitted SSC symbols. Unlike the PSC, which is the same value for each slot, the SSC can take on one of seventeen possible values in each slot. Thus, in order to accumulate the SSC data it is necessary to accumulate the samples from slots of different frames. The SSC sequence in the eighth slot of a frame will not necessarily be the same as the SSC sequence in the ninth slot in that frame. However, the SSC sequence in the eighth slot of a given frame is the same as the SSC sequence in the eighth slot of the subsequent frame and can be meaningfully accumulated.
Multiplexer 31 receives the samples collected over multiple frame periods, each frame period coinciding with 16 consecutive slots. Multiplexer 31 provides the first 256 samples of each slot (part 1 of the slot containing the SSC sequence) to one of sixteen possible SSC inner code detectors 18, which function similarly to PSC detector 12. At the start of accumulating samples for SSC decoding, the SSC buffer 19 within each SSC inner code detector 18 is cleared by setting all elements to zero. Also, switches 20 are configured such that the values output by summers 19 are stored back into SSC buffers 21.
From the first frame period, part 1 of the first slot period is provided to SSC inner code detector 18a, part 1 of the second slot period is provided to SSC inner code detector 18b, and so on until part 1 of the sixteenth slot period is provided to SSC inner code detector 18p. During the second frame period, part 1 of the first slot period is again provided to SSC inner code detector 18a, part 1 of the second slot period is provided to SSC inner code detector 18b, and so on until part 1 of the sixteenth slot period is provided to SSC inner code detector 18p. In this way, the SSC sequences corresponding to each of the sixteen slots in each frame are accumulated over multiple frame periods.
After accumulating the SSC samples, switch 20 toggles to provide the stored accumulated samples from SSC buffer 21 to correlator 22. Correlator 22 computes the correlation energy between the accumulated samples and each of the seventeen possible legitimate sequences (c1, c2, . . . , c17) and provides the correlation energy to maximum detector (MAX DETECT) 23. Maximum detector 23 selects the legitimate sequence with the highest correlation energy and provides the sequence to SSC Outer Decoder 24. Upon receiving the sixteen sequence estimates from each of SSC inner code detectors 18, SSC outer decoder 24 determines the most likely transmitted sixteen element code word.
SSC outer decoder 24 converts the sequence estimates to code word elements (c1, c2, . . . , c17) and then compares the resulting code word to all legitimate code words and all cyclic-shifted versions of those legitimate code words. Upon selection of the most likely transmitted code word, the SSC Outer decoder has detected the frame timing and has decoded the group identification (GI) of the base station.
At this point, samples are stored to allow for pilot channel acquisition, the last of three steps toward acquiring base station timing. The pilot is a continuous orthogonal Gold code that has the broadcast data and PSC/SSC channel data punctured into the first half of every slot. The start of frame timing is used to reduce the amount of memory needed to perform acquisition of the orthogonal Gold code used to spread transmissions by the base station. Half frame buffer 27 stores only the second half of each slot in a frame, this being the portion not punctured by other information. Half frame buffer 27 stores 20,480 samples.
The decoded Group Identification is provided to Orthogonal Gold Code generator (OGC GEN) 25. In response to the Group Identification, Orthogonal Gold Code generator 25 selects a set of sixteen possible masks. A single polynomial is used to generate the sequences and ten millisecond truncated portions of that sequence that are used to perform the spreading operation. The particular portions of the sequence that are used for the spreading are selected by means of a masking operation that is well known in the art and described in detail in U.S. Pat. No. 5,103,459, entitled xe2x80x9cSYSTEM AND METHOD FOR GENERATING SIGNAL WAVEFORMS IN A CDMA CELLULAR TELEPHONE SYSTEMxe2x80x9d, assigned to the assignee of the present invention and incorporated by reference herein.
Generator 25 generates a 40,960-chip orthogonal Gold code sequence, which would be the sequence used to spread a ten millisecond transmission. The sequence from generator 25 is provided to gating element 26. Gating element 26 gates out the first half of each 625 xcexcs period of the sequence output by generator 25 corresponding to the portions of the pilot channel punctured out by the PSC/SSC and broadcast common channel data in the transmission of the PERCH channel.
The gated sequences from gating element 26 are provided to correlator 28. Correlator 28 calculates the correlation between the locally generated and gated orthogonal Gold code sequence and the samples stored in half frame buffer 27. The correlation energy for each potential offset is provided to maximum detector 29. Because the receiver has already acquired frame level timing and because the Orthogonal Gold code sequence is reset at frame boundaries the only sixteen offset hypotheses (O1, O2. . . , O16) need to be tested.
After testing the sixteen possible offset hypotheses, maximum detector 29 outputs the most likely offset. With the frame timing information and the mask used to perform the spreading, the receiver is now capable of receiving the paging channel and beginning two way communications with the transmitting base station.
In the current WCDMA proposal, PSC, SSC, and pilot offset decoding are attempted in a fixed number of frame periods until synchronization is achieved. Six frame periods at a time are analyzed, with the first three frames being used to estimate PSC slot timing, the next two frames being used to decode the SSC code word, and the last frame being used to decode the pilot. Each time one of these six-frame period elapses without satisfactory decoding of PSC, SSC, and pilot, the process starts anew with another six frames. Because the PSC and SSC sequences are transmitted at such low power compared with other parts of the frame, many such sets of frame periods typically elapse before all three types of information are successfully decoded in one set.
The problem with this method of acquiring synchronization is that it takes an average of 500 milliseconds to successfully acquire a WCDMA channel this way. This is much longer than the 200-milliseconds generally allowed in successfully completing a handoff in current CDMA wireless systems, and may result in calls dropping from unsuccessful handoff operations. Therefore, there is a need felt in the art for a method of more rapidly acquiring synchronization in a WCDMA communication system.
The present invention may be used to acquire synchronization in a WCDMA communication system more quickly than currently proposed methods. Various embodiments of the invention utilize longer PSC and SSC sample accumulation periods and parallel decoding of PSC, SSC and pilot information to minimize the time required for synchronization.
The prior art method described above creates an estimate of PSC slot timing based on three frame periods of samples. If that estimate of slot timing turns out to be incorrect, subsequent decoding of SSC and pilot information will fail, and the collection of SSC samples begins anew. The samples used to form previous three-frame estimates of slot timing are discarded when forming subsequent three-frame slot timing estimates.
Embodiments of the invention allow longer PSC sample accumulation periods, instead of forcing a possibly inaccurate decision based on a few frames. Embodiments of the invention also incorporate tests for evaluating the validity of PSC slot timing estimates formed from accumulated samples. Further included are methods of continually accumulating PSC samples until a valid slot timing estimate is achieved. As only the PSC sequence is identical for every slot, accumulation of samples in a slot-wide buffer causes the PSC sequence to rise above the field of other accumulated values. As a slot timing estimate is generated which is the xe2x80x9cbest guessxe2x80x9d at slot timing, but which does not pass the validity test, it is used as a reference for preliminary SSC sample accumulation. If this xe2x80x9cbest guessxe2x80x9d slot timing estimate is later validated by passing the test, then the SSC samples accumulated are used in decoding the SSC code word. This parallel sample accumulation enables embodiments of the invention to accomplish more reliable decoding of the SSC code word after a shorter sample accumulation period.
Embodiments of the invention further incorporate parallel processing of the SSC code and the pilot offset. The SSC decoding process also involves a validity test, but generate an intermediate xe2x80x9cbest guessxe2x80x9d SSC code, which is used to estimate the pilot offset. If subsequent sample accumulation of the SSC code supports the validity of the xe2x80x9cbest guessxe2x80x9d SSC code, then the corresponding pilot offset estimate may be immediately used. This method is called parallel, because the pilot offset is decoded simultaneously with the SSC.
In the various embodiments of the present invention, parallel processing of accumulated sample values lead to quicker synchronization with a WCDMA channel. Utilizing these embodiments, synchronization may be achieved in as little as 10 or 30 milliseconds for a strong received signal level. Even if the received signal is weak, however, the more efficient use of accumulated samples allowed by the present invention leads to faster synchronization than the prior art techniques.